When we plugged in Adapter19VIN, the power flows to have a 5VPCU, 3VPCU voltage,
it is by the PU10 (MAX1999) automatically generated, then the machine is in standby
mode.
When we press the Power Button, NBSWON # moment there is a low level, which gave
low 97551,97551 received signal to generate signals DNBSWON #, DNBSWON
distributed to South Bridge, also issued S5-ON 11th pin to 1845 produce 1.5V_S5. S5-
ON input PQ128 PQ132 generated through S5-OND.
S5-OND and PQ141 PQ127 were generated by 5V_S5 and 3V_S5.
3V_S5, 5V_S5, 1.5V_S5 time power to the South Bridge.
South Bridge received DNBSWON low, it occurs SUSB #, SUSC # 2 high sent to 97551,
97551 received SUSB #, SUSC # after have had a SUSON, MAINON #, VRON. SUSON
signals into SUSD signal sent PQ143, PQ145 tube arises 3VSUS, 5VSUS, and SUSON
sent to MAX1845 generate 2.5VSUS.
MAINON # generated by PU7 SMDDR-VTERM. At the same time and by PQ119 PQ125
into MAIND send PQ143, PQ145, PQ148, PQ153 produce +3 V, +5 V, +2.5 V, +1.5 V
voltages.
VRON gave PU9 (MAX1907), PU5 (1992E) generated VCC-CORE and VCCP voltage.
PU6, PU4 signals generated HWPG to 97,551, then PU3, PU5 also various feedback
signals to generate a HWPG 97551.
At this point the M / B of the main voltage in each group have been OK back HWPG
voltage feedback signal with convergence, the equivalent of a HWPG "and" relationship,
such as including any group for the low feedback HWPG this POWER OK 97551 occurs
when the instruction to turn off opening of voltage, such as the OK is HWPG constant as
high as 97,551, after receiving HWPG produce PWROK signal sent to SB Southbridge,
Southbridge SB produced after the PCI RST # generated through U42 PCIRST # passed to
North Bridge. North Bridge before they produce the CPURST #.
it is by the PU10 (MAX1999) automatically generated, then the machine is in standby
mode.
When we press the Power Button, NBSWON # moment there is a low level, which gave
low 97551,97551 received signal to generate signals DNBSWON #, DNBSWON
distributed to South Bridge, also issued S5-ON 11th pin to 1845 produce 1.5V_S5. S5-
ON input PQ128 PQ132 generated through S5-OND.
S5-OND and PQ141 PQ127 were generated by 5V_S5 and 3V_S5.
3V_S5, 5V_S5, 1.5V_S5 time power to the South Bridge.
South Bridge received DNBSWON low, it occurs SUSB #, SUSC # 2 high sent to 97551,
97551 received SUSB #, SUSC # after have had a SUSON, MAINON #, VRON. SUSON
signals into SUSD signal sent PQ143, PQ145 tube arises 3VSUS, 5VSUS, and SUSON
sent to MAX1845 generate 2.5VSUS.
MAINON # generated by PU7 SMDDR-VTERM. At the same time and by PQ119 PQ125
into MAIND send PQ143, PQ145, PQ148, PQ153 produce +3 V, +5 V, +2.5 V, +1.5 V
voltages.
VRON gave PU9 (MAX1907), PU5 (1992E) generated VCC-CORE and VCCP voltage.
PU6, PU4 signals generated HWPG to 97,551, then PU3, PU5 also various feedback
signals to generate a HWPG 97551.
At this point the M / B of the main voltage in each group have been OK back HWPG
voltage feedback signal with convergence, the equivalent of a HWPG "and" relationship,
such as including any group for the low feedback HWPG this POWER OK 97551 occurs
when the instruction to turn off opening of voltage, such as the OK is HWPG constant as
high as 97,551, after receiving HWPG produce PWROK signal sent to SB Southbridge,
Southbridge SB produced after the PCI RST # generated through U42 PCIRST # passed to
North Bridge. North Bridge before they produce the CPURST #.
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