Power management chips and BIOS chips, where 3.3VPCU, VC CRT C where
normal electricity supply, will enter the working state. One-chip power
management system can be understood as moments in the work of the monitoring
status. Connected to the power management chip clock oscillator Y6 external
power management chip to monitor the line to provide the basis 32.768kHz clock
signal. If you do not have this clock signal, the power management chip will also
be in a "paralyzed" state. -
Power Management IC 2 feet for the start signal to detect motion foot NBSWON #.
Under normal circumstances, when the pin is detected over a negative pulse
signal, the chip that was press the power button on the boot, and immediately turn
signal through the first 4PIN of DNBSWON # "reported to the South Bridge chips."
South Bridge chip part of the line is always in working condition. Likewise, it is
also connected to a 32.768kHz external when Zhong Jingzhen Y5, its role is to
South Bridge chip modules RTC and basic detection module reference clock.
Southbridge chip power management chip receiving the boot action to issue a
pulse signal, this chip will be the first 26PIN the S USB #, the first 69PIN high of
SUSC # set to an invalid state, the power management chip, boot up action to
provide necessary conditions.
Power management chip in the receiver to the South Bridge chip SUSB #, SUSC
# control signal "Reply" In the future, it began to issue secondary power control
signal (S5-ON, SUSON , MAINON, VRON) to each computer motherboard chip
supply voltage generated.
DC / DC power supply generating circuit will have all the appropriate supply
voltage to achieve stability in their output will be issued PWRGD high effective
signal back to the power management chip, meaning that tell it, had now been
given the task of successfully completed. Next, the power management chip
control chip can be reported to the superior work. 4 Z5 c-u $ d5 @.] - G1 D
When the power management chip to the PWRGD signal received after certain
Delay period, to again PWROK signal to the corresponding delay circuit. Delay
circuits at different delay, the order issued by the appropriate power supply OK
signal. One, SB-PWROK signal to the South Bridge chip, NB-PWROK signal to
the North Bridge chip, CPU-PWROK signal to CPU. Next, the system chipset will
issue a reset signal, first issued by the South Bridge PCI RST # signal to the PCI
bus and other related equipment and the North Bridge chip. Meanwhile, the North
Bridge chip in the receiver to the South Bridge chip issued PCIRST # reset signal,
we will send CPURST # signal to the CPU.
normal electricity supply, will enter the working state. One-chip power
management system can be understood as moments in the work of the monitoring
status. Connected to the power management chip clock oscillator Y6 external
power management chip to monitor the line to provide the basis 32.768kHz clock
signal. If you do not have this clock signal, the power management chip will also
be in a "paralyzed" state. -
Power Management IC 2 feet for the start signal to detect motion foot NBSWON #.
Under normal circumstances, when the pin is detected over a negative pulse
signal, the chip that was press the power button on the boot, and immediately turn
signal through the first 4PIN of DNBSWON # "reported to the South Bridge chips."
South Bridge chip part of the line is always in working condition. Likewise, it is
also connected to a 32.768kHz external when Zhong Jingzhen Y5, its role is to
South Bridge chip modules RTC and basic detection module reference clock.
Southbridge chip power management chip receiving the boot action to issue a
pulse signal, this chip will be the first 26PIN the S USB #, the first 69PIN high of
SUSC # set to an invalid state, the power management chip, boot up action to
provide necessary conditions.
Power management chip in the receiver to the South Bridge chip SUSB #, SUSC
# control signal "Reply" In the future, it began to issue secondary power control
signal (S5-ON, SUSON , MAINON, VRON) to each computer motherboard chip
supply voltage generated.
DC / DC power supply generating circuit will have all the appropriate supply
voltage to achieve stability in their output will be issued PWRGD high effective
signal back to the power management chip, meaning that tell it, had now been
given the task of successfully completed. Next, the power management chip
control chip can be reported to the superior work. 4 Z5 c-u $ d5 @.] - G1 D
When the power management chip to the PWRGD signal received after certain
Delay period, to again PWROK signal to the corresponding delay circuit. Delay
circuits at different delay, the order issued by the appropriate power supply OK
signal. One, SB-PWROK signal to the South Bridge chip, NB-PWROK signal to
the North Bridge chip, CPU-PWROK signal to CPU. Next, the system chipset will
issue a reset signal, first issued by the South Bridge PCI RST # signal to the PCI
bus and other related equipment and the North Bridge chip. Meanwhile, the North
Bridge chip in the receiver to the South Bridge chip issued PCIRST # reset signal,
we will send CPURST # signal to the CPU.
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