1 . Battery 3V voltage over RB resistance renamed VBAT, all the way to the IO chip 100 feet , for the detection of battery power . Another way to D1 of a foot , from 3 feet out RTCVDD, to PCH provides real-time clock supply .
2 . RTCVDD by R239 renamed DSWVRMEN to PCH, open PCH Deep Sleep powered internal 1.05V regulator work .
RTCVDD by R236 renamed INTVRMEN, to PCH, open PCH internal 1.05V standby power regulator work .
RTCVDD by R237 , C92 delay circuit, the delay to get real-time clock reset signal -RTCRST to PCH , and connected to CLR_CMOS jumpers.
RTCVDD by R234 , C91 delay circuit, the delay to obtain a second real-time clock reset signal -SRTCRST to PCH .
3.PCH to 32K crystal power, since the crystal oscillator generates 32.768KHz frequency to PCH .
4 . Plug ATX power supply, power output 5VSB , through Q64 buck get 3.3V of 3VDUAL_PCH voltage to PCH 's VCCDSW3_3 feet deep sleep to provide power to the bridge.
5 . 3VDUAL over R285 , to Q39 of B pole, control Q41 is turned on, so that Q39 is turned off by R267 pull to get the 3.3V high PCH_DPWROK signal is sent to the PCH expressed deep sleep supply is normal.
6 . 5VSB by Q58 convert 5VDUAL power, 5VDUAL then through Q61 buck, get 3VDUAL voltage to PCH 's VCCSUS3_3 feet, IO of 98 feet, PCI 's A14 foot, PCIE of B10 feet provide standby power.
7 . IO chip from 116 output pin -RSMRST # signal, via R236 pullup for 3.3V high to PCH , said board standby power supply is normal.
8 . Shorting switch pin high level trigger signal transitions -PWRBT_1 , over R175 resistance renamed -PWRBTSW , to the IO chip 106 feet.
9 . IO chip via internal conversion from 103 feet high output level transitions PWRBTSW signal to PCH request on electricity.
10 . PCH from BN52 emits a continuous high level of foot -S4_s5 signals over MDR41 resistance to MQ6 of B pole, control MQ6 conduction, so MQ4 off, get a high level of DDR_EN signal, open the memory power supply circuits.
11 . PCH from BN53 issued by foot sustained high level of -SLP_S3 , -SLP_A signal, -SLP_S3 to the IO chip 102 feet, indicating that allow electricity.
12 . IO chip from 107 emits a continuous low-level foot -PSON signal attached to ATX power connector 16 feet.
13 . ATX Power 16 feet (green line) after being pulled low power output 5V , 12V , 3.3V and other main power supply, complete the power.
14 . 12V from D5 positive input from the negative output, over R381 resistance to U8 's 5 foot power. U8 through the internal diodes give a foot. When MQ4 cut-off, U8 chip seven feet high began to pull to get the chip to work through internal. From 2 feet and 4 feet out on the tube and down tube drivers drive signals to control Q53 , Q52 alternately turn, will 5VDUAL down through L3 and after the output filter capacitor 1.5V of DDR_15V memory power.
15 . VCC over R374 to U6 of 5 , 6 , 7 , 8 pin power supply, DDR_15V to U6 of a foot-powered, DDR_15V by R324 , R341 partial pressure get 0.75V voltage, to U6 of 3 feet, U6 started working from 4 feet output 0.75V memory load power DDRVTT .
16 . 3VDUAL to U9 's 3 pin power supply, 5VDUAL over R664 to U9 the 4 pin power supply. PCH output -SLP_A high signal over R671 , R670 renamed 1_05ME_EN to U9 's two feet, U9 start working from 6 feet out 1.05V of VCC1_05_ME power to PCH 's ME module.
17 . -SLP_A , VCC1_05_ME , VCC3_ME joint control Q86 conduction, Q85 deadline, after R673 pullup get 3.3V of ME_PWROK signal to PCH , said the ME supply is normal. (In BIOS opens in AMT feature, the standby bridge on the issue -SLP_A signal turns ME supply, if closed AMT when the function, -SLP_A signal -SLP_S3 signal synchronization)
18 . 5VDUAL over R330 to Q42 , by Q42 buck get 2.5V of 2_5LEVEL . 2_5LEVEL by R191 , R192 partial pressure get 1.05V of VCC1_05_EN , sent U1B of 5 feet, U1B the 5 pin voltage is greater than 6 feet voltage, 7 feet high output, control Q35 is turned on, DDR_15V through Q35 buck, get 1.05 V 's VCC1_05_PCH bridge supply.
19 . 2_5LEVEL by R189 , R188 partial pressure get 1.8V of VCC18_EN , to U1A of 3 feet, U1A the 3 -pin voltage is greater than 2 feet voltage, an output pin high, control Q26 is turned on, VCC3 through Q26 buck, get 1.8V of VCC1_8_PCH bridge supply.
20 . VCC through the TR1 resistance to TU1 of 5 foot-powered, TU1 through the internal diode to a foot-powered. VCC1_05_PCH over R154 to Q20 of B pole, control Q20 is turned on, so that Q16 is turned off. TU1 of 7 feet inside pull to get on VTT_EN high, TU1 start working from 2 feet and 4 feet out on the tube and down tube drivers drive signals to control TQ2 , TQ3 alternately turned on, the 12V ( VIN ) buck by TL1 and after the output filter capacitor CPU_VTT bus powered ( 1.05V ).
21 . 2_5LEVEL by R111 , R153 partial pressure get 0.9V or so VSA_REF , sent U1C of 10 feet, 10 feet voltage is greater than 9 feet voltage, 8 feet high output control Q8 is turned on, CPU_VTT by Q8 antihypertensive agents get the system voltage VCCSA .
22 . VCC through the DR457 , DR458 to DU1 of 25 , 26 foot power, DU1 through internal to the BOOT pin power supply. Replace the CPU after, CPU set SVAD of SCLK , SDA line high and low. VCCSA over R139 to Q21 of B pole, control Q21 is turned on, so that Q17 is turned off by R115 pull to get on 1.05V high level VTT_PWRGD signals sent DU1 of 9 feet to open the chip work. DU1 outputs UGATE , LGATE , PWM3 signal control MOS alternately turned on, the 12V (VIN) to get buck CPU core power supply VCORE .
23 . VCORE stabilized DU1 from 19 feet out VR_RDY signal through the DR85 pullup to 3.3V high, too DR91 to DQ18 of B pole, control DQ18 conduction, so DQ19 deadline, the DR109 , DR110 pull on the partial pressure, get 3.267V high level PCH_CRMPWRGD signal to PCH 's BJ35 feet ( SYS_PWROK ), said the CPU power supply is normal.
24 . ATX power supply delays from 8 feet issued 5V high level PWROK signals sent IO chip 50 feet. IO chip converted from 63 feet issued ITE_PWROK1 by R52 pulled on 3.3V high, over R51 renamed PWROK1 , to PCH 's BJ38 feet ( PWROK ), said the motherboard power supply is normal.
25 . PCH internal clock voltage starts to work, the output clock signal to the CPU , IO , network cards, PCI , PCI-E and other equipment.
26 . SYS_PWROK , PWROK at PCH the internal phase, from BG46 issued feet DRAM_PWROK signal, the R246 pullup for 1.5V high, given CPU memory modules, indicating that the motherboard power supply is normal.
27 . PCH from BD53 issued feet CPUPWROK signal sent to CPU board, said power supply is normal.
28 . PCH power, clock, normal, from BK48 issued feet -PFMRST platform reset signal, via R61 pullup to 3.3V high to IO chip 68 feet, reset IO chip.
29 . PCH from AV14 issued feet -PCIRST_F signals over R448 renamed -PCIRST reset the PCI slot.
30 . IO chip power supply, clock, reset normal delay from 64 feet issued -PFMRST # 2 signal resets the card, from 115 feet to issue -PCIE_RST reset the PCI-E slot.
31 . Finally, the internal conversion from 65 feet issued PRST1- signal, over R78 renamed -PFMRST1 , and then the R77 pullup to 3.3V high. -PFMRST1 over R217 resistance to Q33 of B pole, control Q33 is turned on, so that Q34 is turned off. VCC3 through R215 , R216 partial pressure obtained 1.1V high level -CPURST signal is sent to the CPU 's F36 pin reset CPU .
32 . CPU power, clock, PG , reset to normal, start reading the BIOS program, the Power On Self-Test.
33 . CPU issue SVID signal to DU1 , DU1 driving signal control DQ13 , DQ15 , DQ14 work will VIN get buck graphics power CPU_VAXG .
2 . RTCVDD by R239 renamed DSWVRMEN to PCH, open PCH Deep Sleep powered internal 1.05V regulator work .
RTCVDD by R236 renamed INTVRMEN, to PCH, open PCH internal 1.05V standby power regulator work .
RTCVDD by R237 , C92 delay circuit, the delay to get real-time clock reset signal -RTCRST to PCH , and connected to CLR_CMOS jumpers.
RTCVDD by R234 , C91 delay circuit, the delay to obtain a second real-time clock reset signal -SRTCRST to PCH .
3.PCH to 32K crystal power, since the crystal oscillator generates 32.768KHz frequency to PCH .
4 . Plug ATX power supply, power output 5VSB , through Q64 buck get 3.3V of 3VDUAL_PCH voltage to PCH 's VCCDSW3_3 feet deep sleep to provide power to the bridge.
5 . 3VDUAL over R285 , to Q39 of B pole, control Q41 is turned on, so that Q39 is turned off by R267 pull to get the 3.3V high PCH_DPWROK signal is sent to the PCH expressed deep sleep supply is normal.
6 . 5VSB by Q58 convert 5VDUAL power, 5VDUAL then through Q61 buck, get 3VDUAL voltage to PCH 's VCCSUS3_3 feet, IO of 98 feet, PCI 's A14 foot, PCIE of B10 feet provide standby power.
7 . IO chip from 116 output pin -RSMRST # signal, via R236 pullup for 3.3V high to PCH , said board standby power supply is normal.
8 . Shorting switch pin high level trigger signal transitions -PWRBT_1 , over R175 resistance renamed -PWRBTSW , to the IO chip 106 feet.
9 . IO chip via internal conversion from 103 feet high output level transitions PWRBTSW signal to PCH request on electricity.
10 . PCH from BN52 emits a continuous high level of foot -S4_s5 signals over MDR41 resistance to MQ6 of B pole, control MQ6 conduction, so MQ4 off, get a high level of DDR_EN signal, open the memory power supply circuits.
11 . PCH from BN53 issued by foot sustained high level of -SLP_S3 , -SLP_A signal, -SLP_S3 to the IO chip 102 feet, indicating that allow electricity.
12 . IO chip from 107 emits a continuous low-level foot -PSON signal attached to ATX power connector 16 feet.
13 . ATX Power 16 feet (green line) after being pulled low power output 5V , 12V , 3.3V and other main power supply, complete the power.
14 . 12V from D5 positive input from the negative output, over R381 resistance to U8 's 5 foot power. U8 through the internal diodes give a foot. When MQ4 cut-off, U8 chip seven feet high began to pull to get the chip to work through internal. From 2 feet and 4 feet out on the tube and down tube drivers drive signals to control Q53 , Q52 alternately turn, will 5VDUAL down through L3 and after the output filter capacitor 1.5V of DDR_15V memory power.
15 . VCC over R374 to U6 of 5 , 6 , 7 , 8 pin power supply, DDR_15V to U6 of a foot-powered, DDR_15V by R324 , R341 partial pressure get 0.75V voltage, to U6 of 3 feet, U6 started working from 4 feet output 0.75V memory load power DDRVTT .
16 . 3VDUAL to U9 's 3 pin power supply, 5VDUAL over R664 to U9 the 4 pin power supply. PCH output -SLP_A high signal over R671 , R670 renamed 1_05ME_EN to U9 's two feet, U9 start working from 6 feet out 1.05V of VCC1_05_ME power to PCH 's ME module.
17 . -SLP_A , VCC1_05_ME , VCC3_ME joint control Q86 conduction, Q85 deadline, after R673 pullup get 3.3V of ME_PWROK signal to PCH , said the ME supply is normal. (In BIOS opens in AMT feature, the standby bridge on the issue -SLP_A signal turns ME supply, if closed AMT when the function, -SLP_A signal -SLP_S3 signal synchronization)
18 . 5VDUAL over R330 to Q42 , by Q42 buck get 2.5V of 2_5LEVEL . 2_5LEVEL by R191 , R192 partial pressure get 1.05V of VCC1_05_EN , sent U1B of 5 feet, U1B the 5 pin voltage is greater than 6 feet voltage, 7 feet high output, control Q35 is turned on, DDR_15V through Q35 buck, get 1.05 V 's VCC1_05_PCH bridge supply.
19 . 2_5LEVEL by R189 , R188 partial pressure get 1.8V of VCC18_EN , to U1A of 3 feet, U1A the 3 -pin voltage is greater than 2 feet voltage, an output pin high, control Q26 is turned on, VCC3 through Q26 buck, get 1.8V of VCC1_8_PCH bridge supply.
20 . VCC through the TR1 resistance to TU1 of 5 foot-powered, TU1 through the internal diode to a foot-powered. VCC1_05_PCH over R154 to Q20 of B pole, control Q20 is turned on, so that Q16 is turned off. TU1 of 7 feet inside pull to get on VTT_EN high, TU1 start working from 2 feet and 4 feet out on the tube and down tube drivers drive signals to control TQ2 , TQ3 alternately turned on, the 12V ( VIN ) buck by TL1 and after the output filter capacitor CPU_VTT bus powered ( 1.05V ).
21 . 2_5LEVEL by R111 , R153 partial pressure get 0.9V or so VSA_REF , sent U1C of 10 feet, 10 feet voltage is greater than 9 feet voltage, 8 feet high output control Q8 is turned on, CPU_VTT by Q8 antihypertensive agents get the system voltage VCCSA .
22 . VCC through the DR457 , DR458 to DU1 of 25 , 26 foot power, DU1 through internal to the BOOT pin power supply. Replace the CPU after, CPU set SVAD of SCLK , SDA line high and low. VCCSA over R139 to Q21 of B pole, control Q21 is turned on, so that Q17 is turned off by R115 pull to get on 1.05V high level VTT_PWRGD signals sent DU1 of 9 feet to open the chip work. DU1 outputs UGATE , LGATE , PWM3 signal control MOS alternately turned on, the 12V (VIN) to get buck CPU core power supply VCORE .
23 . VCORE stabilized DU1 from 19 feet out VR_RDY signal through the DR85 pullup to 3.3V high, too DR91 to DQ18 of B pole, control DQ18 conduction, so DQ19 deadline, the DR109 , DR110 pull on the partial pressure, get 3.267V high level PCH_CRMPWRGD signal to PCH 's BJ35 feet ( SYS_PWROK ), said the CPU power supply is normal.
24 . ATX power supply delays from 8 feet issued 5V high level PWROK signals sent IO chip 50 feet. IO chip converted from 63 feet issued ITE_PWROK1 by R52 pulled on 3.3V high, over R51 renamed PWROK1 , to PCH 's BJ38 feet ( PWROK ), said the motherboard power supply is normal.
25 . PCH internal clock voltage starts to work, the output clock signal to the CPU , IO , network cards, PCI , PCI-E and other equipment.
26 . SYS_PWROK , PWROK at PCH the internal phase, from BG46 issued feet DRAM_PWROK signal, the R246 pullup for 1.5V high, given CPU memory modules, indicating that the motherboard power supply is normal.
27 . PCH from BD53 issued feet CPUPWROK signal sent to CPU board, said power supply is normal.
28 . PCH power, clock, normal, from BK48 issued feet -PFMRST platform reset signal, via R61 pullup to 3.3V high to IO chip 68 feet, reset IO chip.
29 . PCH from AV14 issued feet -PCIRST_F signals over R448 renamed -PCIRST reset the PCI slot.
30 . IO chip power supply, clock, reset normal delay from 64 feet issued -PFMRST # 2 signal resets the card, from 115 feet to issue -PCIE_RST reset the PCI-E slot.
31 . Finally, the internal conversion from 65 feet issued PRST1- signal, over R78 renamed -PFMRST1 , and then the R77 pullup to 3.3V high. -PFMRST1 over R217 resistance to Q33 of B pole, control Q33 is turned on, so that Q34 is turned off. VCC3 through R215 , R216 partial pressure obtained 1.1V high level -CPURST signal is sent to the CPU 's F36 pin reset CPU .
32 . CPU power, clock, PG , reset to normal, start reading the BIOS program, the Power On Self-Test.
33 . CPU issue SVID signal to DU1 , DU1 driving signal control DQ13 , DQ15 , DQ14 work will VIN get buck graphics power CPU_VAXG .
